Halo-free non-rectifying contact on chip with halo source/drain diffusion

ABSTRACT

A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention generally relates to diffusions in devices on highperformance semiconductor integrated circuit chips. More particularly,it relates to halo implants for such integrated circuit chips.

[0003] 2. Background of the Invention

[0004] Symmetric and asymmetric halo implants have been suggested toimprove performance of low power short channel length field effecttransistors (FET) by improving resistance to punch through. Symmetrichalo implants are pockets of increased dopant concentration of the sameconductivity type as the channel region in areas adjacent to the FETsource and drain edges. Each of these FET halo implants is dopedopposite to the adjacent source/drain diffusion. Asymmetric haloimplants extend adjacent to either the source or the drain or they mayextend differently adjacent the source than adjacent the drain. Haloimplants may also extend into or under the channel region adjacent thesource or drain edges. It is believed that further improvement of haloimplants are attainable that will provide further improvement in deviceand chip performance, and one solution is provided by the followinginvention.

BRIEF SUMMARY OF THE INVENTION

[0005] It is an object of the present invention to avoid a halo implanton non-rectifying contacts of devices on chips having FET devices withhalo implants.

[0006] It is a further object of the present invention to avoid a haloimplant on non-rectifying contacts of gate conductor defined resistors,capacitors, lateral diodes, lateral SOI diodes, and FET body contacts onchips having FET devices with halo implants.

[0007] It is a feature of the present invention that no special mask isneeded to avoid halo implants on non-rectifying contacts.

[0008] It is a another feature of the present invention that a lateralSOI gated diode, such as those used for overshoot/undershoot clamping,ESD protection, and temperature sensing, has no halo diffusion in one orboth diffusion contacts.

[0009] It is an advantage of the present invention that the avoidance ofhalo implants on non-rectifying contacts improves series resistance andperformance of devices on integrated circuits having FETs with haloimplants.

[0010] It is another advantage of the present invention that theavoidance of halo implants on non-rectifying contacts improves yield ofintegrated circuit chips having FETs with halo implants.

[0011] These and other objects, features, and advantages of theinvention are accomplished by a semiconductor chip, comprising asemiconductor substrate. A rectifying contact diffusion and anon-rectifying contact diffusion are in the substrate. A halo diffusionis adjacent the rectifying contact diffusion and no halo diffusion isadjacent the non-rectifying contact diffusion.

[0012] The structures are suitable for forming body contacts to FETs,lateral diodes, resistors, and capacitors on chips having FETs withhalos adjacent source or drain diffusions. The structures areparticularly suitable for SOI chips but may also be used for bulksilicon chips.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0013] The foregoing and other objects, features, and advantages of theinvention will be apparent from the following detailed description ofthe invention, as illustrated in the accompanying drawings, in which:

[0014]FIG. 1a is a top view of an FET of the present invention in whichthe FET has source/drain diffusions and a body contact adjacent a gate,in which the source/drain diffusions have halo implants but the bodycontact does not;

[0015]FIG. 1b is a top view of an FET similar to the FET of FIG. 1a, butwith a T-shaped gate;

[0016]FIG. 1c is a bent cross sectional view through the device of FIG.1a along line 1 c-1 c′;

[0017]FIG. 2a is a top view of a lateral diode of the present inventionin which the diode has a rectifying diffusion and a non-rectifyingdiffusion adjacent gate conductor, in which the rectifying diffusion hasa halo implant but the non-rectifying diffusion does not;

[0018]FIG. 2b is a cross sectional view through the device of FIG. 2a;

[0019]FIG. 2c is a top view of a lateral diode of the present inventionin which the diode includes a rectifying diffusion and a non-rectifyingdiffusion adjacent gate conductor, in which neither the rectifyingdiffusion nor the non-rectifying diffusion has a halo implant;

[0020]FIG. 3a is a graph of I-V characteristics comparing forward biaseddiodes with and without halo implants adjacent the non-rectifyingdiffusions;

[0021]FIG. 3b is a graph of resistance v. gate to source voltage,showing the irregular change in resistance for SOI FETS with a haloimplant adjacent the non-rectifying body contact diffusion;

[0022]FIG. 4a is a cross sectional view of a device of the presentinvention in which the device has two non-rectifying junctions withouthalo implants adjacent gate conductor, in which the device can serve asa resistor or as a capacitor; and

[0023]FIG. 4b is a cross sectional view of a prior art device having twonon-rectifying junctions with halo implants in which the device canserve as a resistor or as a capacitor.

DETAILED DESCRIPTION OF THE INVENTION

[0024] The present inventors discovered that halo implants used to avoidpunch through on field effect transistor (FET) devices can degradeperformance of devices if the halo implants are also provided adjacentnon-rectifying or ohmic contacts. A non-rectifying contact is used, forexample as a body contact to the FET. A non-rectifying contact is alsoused for a gate conductor defined lateral diode ohmic contact. It canalso be used for gate conductor defined diffusions for resistors andcapacitors that have the same doping as the semiconductor bodyunderlying gate conductor. Contacts are made to such diffusions toprovide a non-rectifying contact to a body region underlying gateconductor or to provide a resistive path to another non-rectifyingcontact to the body. In these cases the halo implants would beoppositely doped to both the diffusions and to the body region under thegate.

[0025] The inventors found that oppositely doped halo regions introducean undesired rectifying region in parallel with the ohmic contact. Thehalo also interferes with the body contact by reducing the area of ohmiccontact or by blocking the ohmic contact. The halo implants thereforealso increase series resistance between the non-rectifying or ohmiccontact and the body or channel region of the device. For FETs controlof the body potential is thereby degraded, and that degrades controlover threshold voltage. This reduces functional test yield and adds tocost of making integrated circuit chips.

[0026] The invention provides halo implants adjacent rectifyingdiffusions, such as source/drain diffusions of FETS while not providinghalo implants for non-rectifying diffusions, such as body contacts toFETS, lateral diodes, and gate defined resistors and capacitors. FET 10and FET 10′ are formed on SOI body 12 on back insulator 14 on bulksubstrate 16, as shown in top view in FIGS. 1a, 1 b and in bent crosssectional view in FIG. 1c. FET 10 includes source/drain diffusions 24,26 adjacent gate 28 or T-shaped gate 28′ on gate dielectric 29.

[0027] In this application a later applied layer may be “on” anotherlayer even if there is an intervening layer and regardless of theorientation the substrate, wafer, or chip is held.

[0028] FET 10 also includes extension diffusions 30, 32 and halodiffusions 34, 36, adjacent source/drain diffusions 24 and body contact38.Halo diffusions 34, 36 are oppositely doped from adjacentsource/drain diffusions 24.

[0029] No halo diffusion doped oppositely to body 12 and body contact 38is provided adjacent body contact 38, substantially reducing seriesresistance and performance degradation that would result from inclusionof a halo there, as shown in FIG. 1c.

[0030] In addition the extension diffusion for body contact 38 isomitted. The extension and halo implants are provided in the samemasking step earlier in the process than the source drain diffusion. Theextension is the same doping type as the source/drain doping but iscloser to the surface and extends under more of the gate. The extensionimplant is usually provided with the ion beam aiming along a normal tothe wafer surface. The halo implant may be aimed normal to the surfaceor at an angle to provide ions under gate 28. Alternatively part of thehalo dose may be provided normal and part at an angle.

[0031] In forming diffusions for FETs on CMOS chips, typically fourmasks are used. One mask is used for both the halo and extensionimplants for p channel devices. This mask blocks n channel devices. Asecond mask is used for both the halo and extension diffusions for nchannel devices. This mask blocks p channel devices. Then spacer 40 isprovided along sidewalls of gate 28. A third mask is used for thesource/drain deep diffusions for the p channel devices. This mask blocksn channel devices. A fourth mask is then used for the source/drain deepdiffusions for the n channel devices. This mask blocks p channeldevices.

[0032] The present invention redesigns the two halo and extension masksto add non-rectifying contacts for FET body contacts, lateral diodes,and gate defined resistors and capacitors to the list of locations beingblocked by the two halo and extension masks. To provide the extensionbut not the halo on body contacts would require another mask. That iswhy both halo and extension implants are blocked. An additional maskcould be used to provide the extension while leaving the halo blocked.

[0033] In the process a blocking mask has a blocking region over thelocation of a non-rectifying diffusion contact. This non-rectifyingdiffusion contact is defined by data on at least one other mask, andtypically as many as three masks are needed to define the non-rectifyingdiffusion contact. The blocking region on the blocking mask is generatedfrom the data on those other masks. The blocking region on the blockingmask is generated from the data on the three other masks by logicallycombining shapes from those three other masks and adjusting the resultto avoid sublithographic features from being formed on the blockingmask. Sublithographic features include notches and slivers having adimension that is less than the smallest dimension that can be resolvedby the photolithographic process. The design of the blocking region iscritical to keeping the halo out of the non-rectifying diffusioncontacts while not being so big that it blocks the halo implant whereneeded.

[0034] In another embodiment of the invention, lateral diode 46 isformed on silicon-on-insulator (SOI) body 12 on back insulator 14. Diode46 includes rectifying diffusion 54 and non-rectifying diffusion 56,both adjacent gate conductor 58, as shown in top view in FIG. 2a and incross sectional view in FIG. 2b. Lateral diode 46 can be used forpurposes such as a phase lock loop circuit, an electrostatic discharge(ESD) protection device, an over voltage clamping network, or atemperature sensing device. Gate conductor 58 is formed of the samematerial as FET gate 28 but does not serve a gate function for a lateraldiode. Rectifying diffusion 54 has extension implant 60 and halodiffusion 62. Non-rectifying diffusion 56 has abrupt p+ to p− ohmiccontact region 64 with no halo implant, substantially improving seriesresistance of diode 46, as shown in FIGS. 3a and 3 b. In addition, thesimplest process for implementing the invention also eliminates anextension implant at non-rectifying diffusion 56. If desired, with anadditional mask, an extension implant (not shown) can be provided alongwith diffusion 56.

[0035] In yet another embodiment of the invention, halo implants areincluded adjacent FET source drain diffusions but lateral diode 46′ hashalo implant 62 omitted from being placed adjacent both rectifyingdiffusion 54′ and non-rectifying diffusion 56, as shown in FIG. 2c.

[0036] Eliminating halo implant 62 from being implanted adjacentrectifying diffusion 54′ increases diode breakdown voltage, reducesdiode forward leakage, improves diode ideality factor and improveslinearity of the exponential IV characteristic. Thus, diode 46′ couldbetter serve several functions on chip, such as temperature measurementand ESD protection. The halo is eliminated from being implanted adjacentrectifying diffusion 54′ by blocking the implant on the halo andextension masks described herein above.

[0037] In yet other embodiments of the invention, resistors andcapacitors are formed without halo implants adjacent diffusions 70 a, 70b, as shown in FIG. 4a. These resistors or capacitors are formed byproviding diffusions adjacent gate conductor 72 on chips that have FETswith the halo implants (see FIG. 1a, 1 b). By comparison, if resistorsand capacitors are formed with halo implants 74 a, 74 b, adjacent gateconductor 72, as shown in prior art FIG. 4b, series resistance is higherand a substantial voltage dependance for that additional seriesresistance is introduced. The end result has been degraded chipperformance. Devices of FIGS. 4a, 4 b are resistors when voltage isprovided between contacts to diffusion 70a and diffusion 70 b. Thedevices are capacitors when a voltage is provided to contacts betweengate conductor 72 and diffusions 70 a, 70 b. If desired, with an extramask, extension implants (not shown) can be provided along withdiffusions 70 a, 70 b.

[0038] While several embodiments of the invention, together withmodifications thereof, have been described in detail herein andillustrated in the accompanying drawings, it will be evident thatvarious further modifications are possible without departing from thescope of the invention. For example, opposite doping types to thoseillustrated are also covered. The invention is also applicable to doublegated FETS in bulk and in SOI technologies. Nothing in the abovespecification is intended to limit the invention more narrowly than theappended claims. The examples given are intended only to be illustrativerather than exclusive.

What is claimed is:
 1. A semiconductor chip, comprising: a semiconductorsubstrate; a rectifying contact diffusion and a non-rectifying contactdiffusion in said substrate; and a halo diffusion adjacent saidrectifying contact diffusion and no halo diffusion adjacent saidnon-rectifying contact diffusion.
 2. A semiconductor chip as recited inclaim 1, wherein said rectifying contact is a source/drain diffusion ofan FET.
 3. A semiconductor chip as recited in claim 1, wherein saidnon-rectifying contact is body contact of an FET, an ohmic contact of alateral diode, a contact of a resistor, or a contact of a capacitor. 4.A semiconductor chip as recited in claim 1, wherein said chip furthercomprises a gate conductor, wherein said rectifying contact is definedby said gate conductor.
 5. A semiconductor chip as recited in claim 1,wherein said chip further comprises a gate conductor, wherein saidnon-rectifying contact is defined by said gate conductor.
 6. Asemiconductor chip as recited in claim 1, wherein said chip furthercomprises a gate conductor, wherein said rectifying contact and saidnon-rectifying contact are both defined by said gate conductor.
 7. Asemiconductor chip as recited in claim 6, wherein said rectifyingcontact is a source/drain diffusion of an FET and wherein saidnon-rectifying contact is a body contact for said FET.
 8. Asemiconductor chip as recited in claim 7, wherein said FET comprises agate conductor, wherein said source/drain diffusions and said bodycontact are all defined by said gate conductor.
 9. A semiconductor chipas recited in claim 8, wherein said FET further comprises a backinsulator and a thin layer of semiconductor on said back insulator. 10.A semiconductor chip as recited in claim 6, wherein said rectifyingcontact is a diffusion of a lateral diode and wherein saidnon-rectifying contact is an ohmic contact to said diode.
 11. Asemiconductor chip as recited in claim 1, wherein said chip furthercomprises an FET comprising a source/drain diffusion and a lateral diodecomprising a rectifying contact diffusion and a non-rectifying contactdiffusion, wherein said rectifying contact is said source/draindiffusion of said FET and said non-rectifying contact is saidnon-rectifying contact diffusion of said lateral diode, and furtherwherein there is no halo diffusion adjacent said rectifying contactdiffusion of said lateral diode.
 12. A semiconductor chip as recited inclaim 1, wherein said chip further comprises a first gate conductor anda second gate conductor, wherein said rectifying contact is defined bysaid first gate conductor and wherein said non-rectifying contact isdefined by said second gate conductor.
 13. A semiconductor chip asrecited in claim 12, further comprising an FET and one of a lateraldiode, a resistor, and a capacitor, wherein said rectifying contact is asource/drain diffusion of said FET and wherein said non-rectifyingcontact is an ohmic contact to said lateral diode, resistor orcapacitor.
 14. A semiconductor chip as recited in claim 13, wherein saidlateral diode is for ESD protection, overshoot/undershoot protection, orover voltage clamping.
 15. A semiconductor chip as recited in claim 13,wherein said lateral diode further comprises a rectifying contactdiffusion, wherein no halo diffusion is adjacent said rectifying contactdiffusion.
 16. A semiconductor chip as recited in claim 1, furthercomprising a second non-rectifying contact, wherein no halo diffusion isadjacent either of said non-rectifying contacts.
 17. A semiconductorchip as recited in claim 1, wherein the chip comprisessilicon-on-insulator.
 18. A semiconductor chip as recited in claim 1,wherein an extension diffusion is adjacent said source drain diffusionand wherein no extension diffusion is adjacent said non-rectifyingcontact.
 19. A method of fabricating a semiconductor chip, comprisingthe steps of: providing a semiconductor substrate; forming a rectifyingdiffusion contact in said substrate; forming a non-rectifying diffusioncontact in said substrate; and forming a halo diffusion adjacent saidrectifying diffusion contact and forming no halo diffusion adjacent saidnon-rectifying diffusion contact.
 20. A method as recited in claim 19,wherein in said forming step (b) said rectifying diffusion is asource/drain diffusion of an FET, wherein in said forming step (c) saidnon-rectifying contact is a body contact for said FET.
 21. A method asrecited in claim 19, wherein said non-rectifying diffusion contact is anelectrode of a lateral diode.
 22. A method as recited in claim 21,wherein said lateral diode is for ESD protection, overshoot/undershootprotection, or over voltage clamping.
 23. A method as recited in claim21, wherein in said forming step (b) said rectifying diffusion is asource/drain diffusion of an FET or a second electrode of said lateraldiode.
 24. A method as recited in claim 19, wherein in said forming step(b) said rectifying diffusion is a source/drain diffusion of an FET,wherein said forming step (c) comprises forming a device having a pairof said non-rectifying diffusion contacts and wherein said step (d)comprises forming no halo diffusion adjacent either of saidnon-rectifying contacts.
 25. A method as recited in claim 24, whereinsaid device comprises a resistor or a capacitor.
 26. A method as recitedin claim 19, wherein in said forming step (a) said substrate comprisesSOI.
 27. A method as recited in claim 19, further comprising forming anextension diffusion adjacent said rectifying contact diffusion andforming no extension diffusion adjacent said non-rectifying contactdiffusion.
 28. A method as recited in claim 19, wherein said formingstep (d) comprises providing a first mask including a location of anon-rectifying diffusion contact, wherein said first mask has a blockingregion over said location.
 29. A method as recited in claim 28, whereinsaid non-rectifying diffusion contact is defined by data on at least oneother mask, and wherein said blocking region on said first mask isgenerated from said data.
 30. A method as recited in claim 29, whereinsaid blocking region on said first mask is generated from said data bylogically combining shapes from a plurality of masks and adjusting theresult to avoid sublithographic features.